diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fb2e1d3..fd16584 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -582,6 +582,8 @@
 	imx6dl-aristainetos2b_7.dtb \
 	imx6dl-aristainetos2b_csl_4.dtb \
 	imx6dl-aristainetos2b_csl_7.dtb \
+	imx6dl-aristainetos2c_4.dtb \
+	imx6dl-aristainetos2c_7.dtb \
 	imx6dl-brppt2.dtb \
 	imx6dl-dhcom-pdk2.dtb \
 	imx6dl-icore.dtb \
diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
new file mode 100644
index 0000000..052d518
--- /dev/null
+++ b/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+ or X11
+/*
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ */
+
+#include <imx6qdl-aristainetos2c-u-boot.dtsi>
+
+&lcd_panel {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ipu_disp>;
+	enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+	backlight = <&backlight>;
+};
diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4.dts b/arch/arm/dts/imx6dl-aristainetos2c_4.dts
new file mode 100644
index 0000000..142b108
--- /dev/null
+++ b/arch/arm/dts/imx6dl-aristainetos2c_4.dts
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * support for the imx6 based aristainetos2c board
+ * parts for 4.3 inch LG display on spi1 port1
+ *
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ *
+ */
+/dts-v1/;
+
+#include "imx6dl-aristainetos2_4.dtsi"
+#include "imx6qdl-aristainetos2c.dtsi"
+
+/ {
+	model = "aristainetos2c i.MX6 Dual Lite Board 4";
+	compatible = "fsl,imx6dl";
+
+};
+
+&ecspi1 {
+	lcd_panel: display@0 {
+		compatible = "lg,lg4573";
+		spi-max-frequency = <10000000>;
+		reg = <1>;
+		power-on-delay = <10>;
+
+		display-timings {
+			480x800p57 {
+				native-mode;
+				clock-frequency = <27000027>;
+				hactive = <480>;
+				vactive = <800>;
+				hfront-porch = <10>;
+				hback-porch = <59>;
+				hsync-len = <10>;
+				vback-porch = <15>;
+				vfront-porch = <15>;
+				vsync-len = <15>;
+				hsync-active = <1>;
+				vsync-active = <1>;
+			};
+		};
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&display_out>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi
new file mode 100644
index 0000000..cb2181d
--- /dev/null
+++ b/arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+ or X11
+/*
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ */
+
+#include <imx6qdl-aristainetos2c-u-boot.dtsi>
+/ {
+	vdd_panel_reg: regulator-panel {
+		compatible = "regulator-fixed";
+		regulator-name = "panel_regulator";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+};
+
+&panel0 {
+	power-supply = <&vdd_panel_reg>;
+};
diff --git a/arch/arm/dts/imx6dl-aristainetos2c_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_7.dts
new file mode 100644
index 0000000..35435e1
--- /dev/null
+++ b/arch/arm/dts/imx6dl-aristainetos2c_7.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * support for the imx6 based aristainetos2c board
+ *
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
+ *
+ */
+/dts-v1/;
+#include "imx6dl-aristainetos2_7.dtsi"
+#include "imx6qdl-aristainetos2c.dtsi"
+
+/ {
+	model = "aristainetos2c i.MX6 Dual Lite Board 7";
+	compatible = "fsl,imx6dl";
+};
diff --git a/arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi
new file mode 100644
index 0000000..88826a2
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+ or X11
+/*
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ */
+
+/ {
+	chosen {
+		u-boot,dm-pre-reloc;
+		stdout-path = &uart2;
+	};
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+	};
+};
+
+&uart2 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_gpio {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart2 {
+	u-boot,dm-pre-reloc;
+};
+
+&iomuxc {
+	u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+	u-boot,dm-pre-reloc;
+};
+
+&backlight {
+	pwms = <&pwm1 0 300000>;
+	default-brightness-level = <2>;
+};
+
+/*
+ * allow switching write protect / reset pin by gpio,
+ * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot
+ */
+&gpio2 {
+	u-boot,dm-pre-reloc;
+
+	wp_spi_nor {
+		gpio-hog;
+		output-high;
+		gpios = <15 GPIO_ACTIVE_HIGH>;
+	};
+
+	reset_spi_nor {
+		gpio-hog;
+		output-high;
+		gpios = <28 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&gpio4 {
+	u-boot,dm-pre-reloc;
+};
+
+&ecspi1 {
+	u-boot,dm-pre-reloc;
+};
+
+&flash {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_ecspi1 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/imx6qdl-aristainetos2c.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi
new file mode 100644
index 0000000..ba13d55
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * support for the imx6 based aristainetos2c board
+ *
+ * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
+ * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
+ *
+ */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
+
+#include "imx6qdl-aristainetos2-common.dtsi"
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio>;
+
+		LED_blue {
+			label = "led_blue";
+			gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
+		};
+
+		LED_green {
+			label = "led_green";
+			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+		};
+
+		LED_red {
+			label = "led_red";
+			gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		LED_yellow {
+			label = "led_yellow";
+			gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+		};
+
+		LED_ena {
+			label = "led_ena";
+			gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ecspi1 {
+	fsl,spi-num-chipselects = <3>;
+	cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH
+		    &gpio4 10 GPIO_ACTIVE_HIGH
+		    &gpio4 11 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	status = "okay";
+	pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+	pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+
+	flash: m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q128a11", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&ecspi4 {
+	fsl,spi-num-chipselects = <2>;
+	cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi4>;
+	status = "okay";
+};
+
+&i2c1 {
+	tpm@20 {
+		compatible = "infineon,slb9645tt";
+		reg = <0x20>;
+	};
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	status = "okay";
+};
+
+&can2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
+	no-1-8-v;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <8>;
+	no-1-8-v;
+	non-removable;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+			/* SS0# */
+			MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
+			/* SS1# */
+			MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1
+			/* SS2# */
+			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1
+			/* WP pin NOR Flash */
+			MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0
+			/* Flash nReset */
+			MX6QDL_PAD_EIM_EB0__GPIO2_IO28  0x4001b0b0
+		>;
+	};
+
+	pinctrl_ecspi4: ecspi4grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
+			MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
+			MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
+			MX6QDL_PAD_EIM_D29__GPIO3_IO29  0x100b1 /* SS0# */
+			MX6QDL_PAD_EIM_A25__GPIO5_IO02  0x100b1 /* SS1# */
+		>;
+	};
+
+	pinctrl_gpio: gpiogrp {
+		fsl,pins = <
+			/* led enable */
+			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x4001b0b0
+			/* LCD power enable */
+			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x4001b0b0
+			/* led yellow */
+			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x4001b0b0
+			/* led red */
+			MX6QDL_PAD_EIM_WAIT__GPIO5_IO00		0x4001b0b0
+			/* led green */
+			MX6QDL_PAD_EIM_A24__GPIO5_IO04		0x4001b0b0
+			/* led blue */
+			MX6QDL_PAD_EIM_EB1__GPIO2_IO29		0x4001b0b0
+			/* Profibus IRQ */
+			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x1b0b0
+			/* FPGA IRQ currently unused*/
+			MX6QDL_PAD_SD3_DAT6__GPIO6_IO18		0x1b0b0
+			/* Display reset because of clock failure */
+			MX6QDL_PAD_SD4_DAT3__GPIO2_IO11		0x4001b0b0
+			/* spi bus #2 SS driver enable */
+			MX6QDL_PAD_EIM_A23__GPIO6_IO06		0x4001b0b0
+			/* RST_LOC# PHY reset input (has pull-down!)*/
+			MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x4001b0b0
+			/* Touchscreen IRQ */
+			MX6QDL_PAD_SD4_DAT1__GPIO2_IO09		0x1b0b0
+			/* PCIe reset */
+			MX6QDL_PAD_EIM_A22__GPIO2_IO16		0x4001b0b0
+			/* make sure pin is GPIO and not ENET_REF_CLK */
+			MX6QDL_PAD_GPIO_16__GPIO7_IO11		0x4001a0b0
+			/* TPM PP */
+			MX6QDL_PAD_EIM_A21__GPIO2_IO17		0x4001b0b0
+			/* TPM Reset */
+			MX6QDL_PAD_EIM_A20__GPIO2_IO18		0x4001b0b0
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
+			MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
+			MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
+		>;
+	};
+
+	pinctrl_usbotg: usbotggrp {
+		fsl,pins = <
+			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID  0x17059
+			MX6QDL_PAD_KEY_COL4__USB_OTG_OC    0x1b0b0
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
+			MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
+			MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+			MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+			MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+			/* SD1 card detect input */
+			MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x1b0b0
+			/* SD1 write protect input */
+			MX6QDL_PAD_DI0_PIN4__GPIO4_IO20		0x1b0b0
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
+			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+			MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
+			MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
+			MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
+			MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
+		>;
+	};
+};
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index de71cd5..f1a1021 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -158,6 +158,17 @@
 	imply CMD_SATA
 	imply CMD_DM
 
+config TARGET_ARISTAINETOS2C
+	bool "Support aristainetos2-revC"
+	select BOARD_LATE_INIT
+	select MX6DL
+	select SYS_I2C_MXC
+	select MXC_UART
+	select FEC_MXC
+	select DM
+	imply CMD_SATA
+	imply CMD_DM
+
 config TARGET_CGTQMX6EVAL
 	bool "cgtqmx6eval"
 	select BOARD_LATE_INIT
diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig
index 9eb3c3b..2ad3dbd 100644
--- a/board/aristainetos/Kconfig
+++ b/board/aristainetos/Kconfig
@@ -33,3 +33,15 @@
 	default 4
 
 endif
+
+if TARGET_ARISTAINETOS2C
+
+source "board/aristainetos/common/Kconfig"
+
+config SYS_BOARD
+	default "aristainetos"
+
+config SYS_BOARD_VERSION
+	default 5
+
+endif
diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS
index 9685c03..b4ca7ab 100644
--- a/board/aristainetos/MAINTAINERS
+++ b/board/aristainetos/MAINTAINERS
@@ -6,6 +6,7 @@
 F:	configs/aristainetos2_defconfig
 F:	configs/aristainetos2b_defconfig
 F:	configs/aristainetos2bcsl_defconfig
+F:	configs/aristainetos2c_defconfig
 F:	arch/arm/dts/imx6qdl-aristainetos2.dtsi
 F:	arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
 F:	arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
@@ -27,3 +28,9 @@
 F:	arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi
 F:	arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi
 F:	arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2c_4.dts
+F:	arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
+F:	arch/arm/dts/imx6dl-aristainetos2c_7.dts
+F:	arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2c.dtsi
+F:	arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 8809079..c79ac1d 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -492,7 +492,8 @@
 	}
 #if ((CONFIG_SYS_BOARD_VERSION == 2) || \
 	(CONFIG_SYS_BOARD_VERSION == 3) || \
-	(CONFIG_SYS_BOARD_VERSION == 4))
+	(CONFIG_SYS_BOARD_VERSION == 4) || \
+	(CONFIG_SYS_BOARD_VERSION == 5))
 	, {
 		.bus	= -1,
 		.addr	= 0,
@@ -520,6 +521,7 @@
 };
 size_t display_count = ARRAY_SIZE(displays);
 
+#if defined(CONFIG_NAND)
 iomux_v3_cfg_t nfc_pads[] = {
 	MX6_PAD_NANDF_CLE__NAND_CLE		| MUX_PAD_CTRL(NO_PAD_CTRL),
 	MX6_PAD_NANDF_ALE__NAND_ALE		| MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -573,6 +575,11 @@
 	/* enable apbh clock gating */
 	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 }
+#else
+static void setup_gpmi_nand(void)
+{
+}
+#endif
 
 int board_init(void)
 {
diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig
index 6f1c825..e26de51 100644
--- a/board/aristainetos/common/Kconfig
+++ b/board/aristainetos/common/Kconfig
@@ -5,6 +5,7 @@
 	  2 version 2
 	  3 version 2b
 	  4 version 2bcsl
+	  5 version 2c
 
 config SYS_I2C_MXC_I2C1
 	default y
diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig
new file mode 100644
index 0000000..46a3cf7
--- /dev/null
+++ b/configs/aristainetos2c_defconfig
@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F_LEN=0xe000
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0xD0000
+CONFIG_TARGET_ARISTAINETOS2C=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_IMX_HAB=y
+# CONFIG_CMD_DEKBLOB is not set
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg"
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run ari_boot"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOARD_TYPES=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_ENCRYPTION=y
+CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb"
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_PINMUX is not set
+# CONFIG_CMD_SATA is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_HASH is not set
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_UBI=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_4"
+CONFIG_OF_LIST="imx6dl-aristainetos2c_4 imx6dl-aristainetos2c_7"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SPI_EARLY=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_OFFSET_REDUND=0xE0000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_APBH_DMA=y
+CONFIG_APBH_DMA_BURST=y
+CONFIG_APBH_DMA_BURST8=y
+CONFIG_DM_GPIO=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_MTD_DEVICE=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_DS1307=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_WATCHDOG=y
+# CONFIG_EFI_LOADER is not set
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
index 64a819d..5f4a4f8 100644
--- a/include/configs/aristainetos2.h
+++ b/include/configs/aristainetos2.h
@@ -128,6 +128,33 @@
 		"${fit_file}\0" \
 	"rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \
 		"${fit_addr_r} ${rescue_fit_file}\0"
+#elif (CONFIG_SYS_BOARD_VERSION == 5)
+#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
+	"emmcpart=1\0" \
+	"emmc_rescue_part=3\0" \
+	"emmcdev=1\0" \
+	"emmcroot=/dev/mmcblk1p1 rootwait rw\0" \
+	"dead=led led_red on\0" \
+	"mtdids=nor0=spi0.0\0" \
+	"mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \
+		"-(ubi-nor)\0" \
+	"addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \
+		"bootmode=${bootmode} mmcpart=${mmcpart} " \
+		"emmcpart=${emmcpart}\0" \
+	"mainboot=echo Booting from eMMC ...; " \
+		"run mainargs addmtd addmisc;" \
+		"if test -n ${addmiscM}; then run addmiscM;fi;" \
+		"if test -n ${addmiscC}; then run addmiscC;fi;" \
+		"if test -n ${addmiscD}; then run addmiscD;fi;" \
+		"run boot_board_type;" \
+		"bootm ${fit_addr_r}\0" \
+	"mainargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${emmcroot} rootfstype=ext4\0 " \
+	"main_load_fit=ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \
+		"${fit_file}; " \
+		"imi ${fit_addr_r}\0 " \
+	"rescue_load_fit=ext4load mmc ${emmcdev}:${emmc_rescue_part} " \
+		"${fit_addr_r} ${rescue_fit_file};imi ${fit_addr_r}\0"
 #else
 #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
 	"dead=led led_red on\0" \